The present invention relates to a semiconductor device in which a bipolar transistor and an insulated gate field effect transistor (hereinafter, "MOS transistor") are formed on a single chip, and more particularly to a method of producing a semiconductor integrated circuit device including a bipolar transistor and an MOS transistor whose substrate region has a conductivity type opposite to that of a collector region of the bipolar transistor.
The integrated circuit including bipolar and MOS transistors is called a Bi-MOS IC and features the high speed operation of bipolar transistors and the high integration density of an MOS transistor. One type of Bi-MOS IC includes both P-channel and N-channel MOS transistors and is known as a Bi-CMOS IC. This device has the advantage of low power consumption in addition to high speed and high integration density.
In an integrated circuit device, regions of the same conductivity type are formed simultaneously in order to reduce manufacturing steps. In a case where the conductivity type of the substrate region of the MOS transistor is different from that of the collector region of the bipolar transistor, source and drain regions of that MOS transistor are formed simultaneously with an emitter region and a collector contact region of the bipolar transistor. The emitter region and the source and drain regions are formed with a shallow junction in order to enhance the integration density. As a result, the collector contact region is similarly made shallow. This causes an increase in the collector resistance of the bipolar transistor. The switching speed thereof is thus lowered.
It is possible to make the collector contact region deeper. However, several additional steps are required for this purpose and the total number of manufacturing steps is greatly increased to raise the manufacturing cost.